Market Map
June 2026
Semiconductors
AI infrastructure — who actually sells inference compute
Inference compute:
the stack
Three layers set the economics — host CPUs orchestrate agents, accelerators generate tokens, memory binds them both. The accelerator layer is splitting into a speed tier (SRAM) and a cost tier (LPDDR), competing with the incumbent Nvidia/AMD + HBM approach.
At scale >$10bn run-rate / deployed at scale
Ramping shipping, early revenue
Pipeline 2026–27 launch
Absorbed IP & talent acquired
01
Host CPUs
Orchestration — agentic workloads are CPU-bound
Nvidia
Grace
Bundled into GB/VR racks — the default host inside Nvidia's own platform.
AMD / Intel
EPYC · Xeon (x86)
Incumbent install base, eroding share — the socket ARM targets.
ARM
AGI CPU · 136-core V3 · 3nm
Meta co-developed; OpenAI, SAP signed. Production H2 '26, material revenue from '28.
Qualcomm
Nuvia server CPU
In development; NVLink-attached. ARM licensee turned ARM competitor.
02
Accelerators
Token generation — speed tier vs cost tier
Merchant
Nvidia
Blackwell → Rubin + ext. HBM
~90% share, >$100bn run-rate. Groq LPU licensed $20bn for low-latency decode.
AMD
Instinct MI + ext. HBM
The only at-scale GPU alternative; multi-billion revenue, second on software.
Cerebras CBRS
WSE-3 · 44GB on-chip SRAM
FY25 rev $248m; IPO May '26 ~$40bn. >$10bn OpenAI pipeline + AWS.
Qualcomm
AI200 '26 · AI250 '27 · LPDDR
Cost tier: 768GB/card for batch & long context. Humain, 200MW from '26.
Groq
LPU · SRAM-resident
IP and leadership absorbed by Nvidia for $20bn; GroqCloud nominally independent. Under antitrust scrutiny.
Absorbed
Captive — in-house silicon
Google
TPU + ext. HBM
Most mature in-house programme; serves Gemini and cloud customers.
AWS
Trainium · Inferentia
Trainium3 paired with Cerebras — prefill on Trainium, decode on wafer.
Meta
MTIA · 4 new chips Mar '26
Accelerators in-house; ARM AGI CPU adopted as drop-in host.
SoftBank
Graphcore IPU → Izanagi
With Ampere CPUs; $450m added May '26. Into Stargate from 2026.
03
Memory
The binding constraint — pricing power sits here
SK Hynix
HBM3E / HBM4
HBM leader, primary Nvidia supplier; sold out through 2026.
Micron
HBM · LPDDR
HBM share gainer; LPDDR feeds the capacity tier.
Samsung
HBM · LPDDR
Closing the HBM qualification gap; LPDDR breadth.
Glossary
HBM high-bandwidth memory, stacked DRAM beside the chip · SRAM static RAM, fastest memory, on-chip · LPDDR low-power DRAM, high capacity at low cost · LPU language processing unit (Groq) · IPU intelligence processing unit (Graphcore) · TPU tensor processing unit (Google) · MTIA Meta training & inference accelerator · WSE wafer-scale engine (Cerebras) · GB/VR Grace-Blackwell / Vera-Rubin rack platforms (Nvidia) · Neoverse V3 ARM's data-centre CPU core design